The present invention relates to system architecture and circuit design of CMOS image sensors. In particular, it is applies to, but it is not restricted to, the photo-detectors and image-sensors described in WO 02/033755.
The performance and functionality of CMOS image sensors depend on the physics of the photo-detection, the modes of operation of the photo-diodes, the in-pixel circuitry, in-pixel circuitry, the circuitry at the periphery, and the interconnects between sensor matrix and the periphery.
WO 02/033755 introduces a process technology that enables Avalanche Photo-Diodes (APDs) to be tightly integrated with CMOS devices for image sensor matrices. Because the active layers of the APDs are epitaxially grown on the substrates, there is the possibility to have optimal doping and heterojunction profiles using silicon-based, such as silicon-germanium (SiGe) and silicon-germanium-carbon (SiGeC), random alloys and superlattices. The epitaxial growth of the active layers allows the fabrication of Separated Absorption and Multiplication Avalanche Photo-Detectors (SAM-APDs), which are perceived to be the photo-diode design that provides the best performance.
The epitaxial growth of the photo-diode layer enables the fabrication of CMOS image sensors on substrates other than bulk silicon wafers, such as Silicon-On-Insulator, including Thin-Film SOI It should be realized that conventional CMOS image sensors cannot be fabricated on TF-SOI because:                1. The crystalline silicon film on top of the buried oxide is too thin to provide useful photo-absorption,        2. In TF-SOI the source/drain-to-well junction, used as the photodiode in conventional CMOS image sensors, does not exist.        
In addition to being the substrate of choice of deep sub-90 nm CMOS devices, with undisputed advantages over bulk substrates/devices, in terms of speed, power dissipation, density of integration, radiation hardness, etc., TF-SOI enable back-side illuminated CMOS image sensors by removing the silicon wafer underneath the buried oxide, and replacing it with a transparent substrate, such as quartz, sapphire, quartz, glass, plastic, etc.
Back-side illumination offers a few unique capabilities to CMOS image sensors, because on the front-side of the wafer, the area above the photo-diode in each pixel no longer needs to be free of opaque materials. Therefore the following become possible:                1. Dense mesh of metal interconnects over the area of the pixels and photo-diodes;        2. In-pixel capacitors, homo-/hetero-junction or MOS capacitors, can be made over the layers of the photo-diodes, thereby avoiding any area penalty;        3. In-pixel MIM capacitors made during the fabrication of dense interconnects over the pixel areas;        4. Light no longer has to travel through the dielectric layers embedded in the metallization stack, thereby removing constrains on the materials, layout, and overall thickness of the metal stack;        5. Without constraints related to image sensing, the number of metal levels used or the fabrication of the CMOS image sensors can be the maximum available to the particular CMOS generation being used. Typically, conventional CMOS image sensors are fabricated with fewer metal levels than a purely electrical circuit made with the same CMOS technology, because of the constraints on the height of the metallization stack.        
Another invention disclosed in a co-pending international application, and designated as Surface Plasmon Polariton (SPP) Light-Funnel, is a new device that considerably changes a few important parameters of image sensors. A matrix of SPP Light-Funnel elements, or SPP pixels, is positioned at the image plane of the lens. Each SPP Light-Funnel gathers light from a certain area, that defines the size of the SPP Pixel, and “funnels it” into a much smaller area, without loss or diffraction. The small cross-section of a SPP Light-Funnel is positioned very near the corresponding photo-diode, which needs to have a surface only slightly larger than the “narrow” region of the Light-Funnel.
The SPP Light-Funnels provide the following possibilities:                1. Light gathered from a certain area, can be forced down to a cross-section much smaller than the wavelength of light, without loss or diffraction.        2. The “narrow” region of a Light-Funnel forces the light into the corresponding photo-diode.        3. The area of the photo-diode can be reduced to only slightly larger than the cross-section of the narrow region of the Light-Funnel, thereby reducing the dark current, without loosing input signal. This results in increased signal-to-noise ratio.        4. The size of the SPP Pixel at the image plane of the lens determines the size of the “Sensor Pixel”.        5. The amount of light coupled into the photo-diode by the Light-Funnel is independent of the size of the photo-diode, thereby providing a constant 100% Fill Factor.        6. Reducing the size of the photo-diode, decreases dark current, and provides extra area for CMOS devices, without decreasing the Fill Factor.        7. Reducing the size of the photo-diode improves the yield of the epitaxial growth process used to fabricate the photo-diodes.        8. Light-coupling mechanism of the SPP Light-Funnel prevents crosstalk between adjacent pixels originated by photons impinging with very oblique paths.        